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| MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3827 group is the 8-bit microcomputer based on the 740 family core technology. The 3827 group has the LCD drive control circuit, the A-D/D-A converter, the UART, and the PWM as additional functions. The various microcomputers in the 3827 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3827 group, refer to the section on group expansion. FEATURES qBasic machine-language instructions ...................................... 71 qThe minimum instruction execution time ........................... 0.5 s (at 8MHz oscillation frequency) qMemory size ROM ................................................................. 4 K to 60 K bytes RAM ................................................................. 192 to 2048 bytes qProgrammable input/output ports ............................................ 55 qOutput port ................................................................................. 8 qInput port .................................................................................... 1 qInterrupts ................................................. 17 sources, 16 vectors (includes key input interrupt) qTimers ........................................................... 8-bit ! 3, 16-bit ! 2 qSerial I/O1 .................... 8-bit ! 1 (UART or Clock-synchronized) qSerial I/O2 ...................................8-bit ! 1 (Clock-synchronized) qPWM output .................................................................... 8-bit ! 1 qA-D converter ............................................... 10-bit ! 8 channels qD-A converter ................................................. 8-bit ! 2 channels qLCD drive control circuit Bias ................................................................................... 1/2, 1/3 Duty ........................................................................... 1/2, 1/3, 1/4 Common output .......................................................................... 4 Segment output ........................................................................ 40 q2 Clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) qWatchdog timer ............................................................ 14-bit ! 1 qPower source voltage ................................................ 2.2 to 5.5 V qPower dissipation In high-speed mode .......................................................... 40 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................................ 60 W (at 32 kHz oscillation frequency, at 3 V power source voltage) qOperating temperature range ................................... - 20 to 85C APPLICATIONS Camera, wireless phone, etc. PIN CONFIGURATION (TOP VIEW) SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 P30/SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35/SEG23 P36/SEG24 P37/SEG25 P00/SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 P10/SEG34 P11/SEG35 P12/SEG36 P13/SEG37 P14/SEG38 P15/SEG39 73 68 56 80 64 63 71 70 58 57 75 65 61 60 77 72 79 67 74 69 62 55 53 76 59 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2 78 66 54 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 13 14 12 28 29 11 15 20 21 16 17 18 19 10 22 25 26 23 24 27 30 1 2 4 5 6 7 3 8 9 50 49 48 47 46 45 44 43 42 M38277M8MXXXFP 41 40 39 38 37 36 35 34 33 32 31 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN XCOUT XCIN RESET P70/INT0 P71 P72 P73 Package type : 100P6S-A (100-pin plastic-molded QFP) Fig. 1 M38277M8MXXXFP pin configuration C1 VL1 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/SCLK22/AN3 P62/SCLK21/AN2 P61/SOUT2/AN1 P60/SIN2/AN0 P57/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/PWM1 P50/PWM0 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43//TOUT P42/INT2 P41/INT1 P40/ADT P77 P76 P75 P74 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) SEG13 SEG14 SEG15 SEG16 SEG17 P30/SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35/SEG23 P36/SEG24 P37/SEG25 P00/SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 P10/SEG34 P11/SEG35 P12/SEG36 P13/SEG37 73 70 67 64 61 58 55 74 71 68 65 62 59 56 75 72 69 66 63 60 57 54 53 52 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2 C1 VL1 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 21 23 24 16 17 10 11 13 18 20 12 14 15 19 22 25 3 6 2 5 1 4 7 8 9 50 49 48 47 46 45 44 43 42 41 40 39 M38277M8MXXXGP M38277M8MXXXHP 38 37 36 35 34 33 32 31 30 29 28 27 26 P14/SEG38 P15/SEG39 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN XCOUT XCIN RESET P70/INT0 P71 P72 P73 P74 P75 P76 Package type : GP........ 100P6Q-A (100-pin plastic-molded LQFP) Package type : HP ........ 100PFB-A (100-pin plastic-molded TQFP) Fig. 2 M38277M8MXXXGP/M38277M8MXXXHP pin configuration 2 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/SCLK22/AN3 P62/SCLK21/AN2 P61/SOUT2/AN1 P60/SIN2/AN0 P57/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/PWM1 P50/PWM0 P47/SRDY1 P46/SCLK1 P45/ TXD P44/RXD P43//TOUT P42/INT2 P41/INT1 P40/ADT P77 FUNCTIONAL BLOCK DIAGRAM Main clock input Reset input RESET VCC VSS (5V) (0V) Main clock output X IN X OUT DA2 DA1 INT0 SI/O2(8) CNTR0,CNTR1 ADT INT1,INT2 P5(8) P4(8) P7(8) P6(8) P3(8) Real time port function XCIN XCOUT VREF AVSS Sub-clock input I/O port P7 I/O port P6 I/O port P5 I/O port P4 Output port P3 I/O port P2 Key input/key-on wake-up interrupt Fig. 3 Functional block diagram Data bus CPU A ROM X Y S PCH Timer X(16) Timer Y(16) D-A2 D-A1 Clock generating circuit RAM VL1 C1 C2 VL2 VL3 X CIN Sub-clock input X COUT LCD display RAM (20 bytes) Sub-clock output LCD drive control circuit COM0 COM1 COM2 COM3 PCL PS Timer 1(8) Timer 3(8) Timer 2(8) Watchdog timer Reset A-D converter (10) PWM(8) SI/O1 (8) TOUT SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 P2(8) P1(8) P0(8) X COUT X CIN I/O port P1 I/O port P0 3827 Group Sub-clock output SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 3 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Table 1 Pin description (1) Pin VCC, VSS VREF AVSS Name Power source Analog reference voltage Analog power source Reset input Clock input Clock output LCD power source Charge-pump capacitor pin Common output Function *Apply voltage of 2.2 V to 5.5 V to VCC, and 0 V to VSS. *Reference voltage input pin for A-D converter and D-A converter. *GND input pin for A-D converter and D-A converter. *Connect to VSS. *Reset input pin for active "L". *Input and output pins for the main clock generating circuit. *Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. *If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. *Input 0 VL1 VL2 VL3 VCC voltage. *Input 0 - VL3 voltage to LCD. *External capacitor pins for a voltage multiplier (3 times) of LCD contorl. *LCD common output pins. *COM2 and COM3 are not used at 1/2 duty ratio. *COM3 is not used at 1/3 duty ratio. SEG0-SEG17 P00/SEG26- P07/SEG33 Segment output I/O port P0 *LCD segment output pins. *8-bit output port. *CMOS compatible input level. *CMOS 3-state output structure. *Pull-up control is enabled. *I/O direction register allows each port to be individually programmed as either input or output. P10/SEG34- P15/SEG39 I/O port P1 *6-bit output port with same function as port P0. *CMOS compatible input level. *CMOS 3-state output structure. *Pull-up control is enabled. *I/O direction register allows each 6-bit pin to be programmed as either input or output. P16, P17 *2-bit I/O port. *CMOS compatible input level. *CMOS 3-state output structure. *I/O direction register allows each pin to be individually programmed as either input or output. *Pull-up control is enabled. *8-bit I/O port with same function as port P0. *Key input (key-on wake-up) interrupt input pins *CMOS compatible input level. *CMOS 3-state output structure. *Pull-up control is enabled. P30/SEG18 - P37/SEG25 Output port P3 *8-bit output port with same function as port P0. *CMOS 3-state output structure. *Port output control is enabled. *LCD segment output pins *LCD segment output pins Function except a port function RESET XIN XOUT VL1-VL3 C1, C2 COM0-COM3 P20 - P27 I/O port P2 4 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 2 Pin description (2) Pin P40/ADT Name I/O port P4 Function *1-bit I/O port with same function as P16 and P17. *CMOS compatible input level. *CMOS 3-state output structure. *7-bit I/O port with same function as P16 and P17. *CMOS compatible input level. *CMOS 3-state output structure. *Pull-up control is enabled. Function except a port function *A-D trigger input pin *Interrupt input pin *Interrupt input pins * clock output pin *Timer 2 output pin *Serial I/O1 I/O pins P41/INT1, P42/INT2 P43//TOUT P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/PWM0, P51/PWM1 P52/RTP0, P53/RTP1 P54/CNTR0, P55/CNTR1 P56/DA1, P57/DA2 P60/AN0/SIN2, I/O port P6 P61/AN1/SOUT2, P62/AN2/SCLK21, P63/AN3/SCLK22 P64/AN4- P67/AN7 P70/INT0 P71-P77 Input port P7 I/O port P7 I/O port P5 *8-bit I/O port with same function as P16 and P17. *CMOS compatible input level. *CMOS 3-state output structure. *Pull-up control is enabled. *PWM function pins *Real time port function pins *Timer X, Y function pins *D-A conversion output pins *8-bit I/O port with same function as P16 and P17. *CMOS compatible input level. *CMOS 3-state output structure. *Pull-up control is enabled. *A-D conversion input pins *Serial I/O2 I/O pins *A-D conversion input pins *1-bit I/O port. *CMOS compatible input level. *7-bit I/O port with same function as P16 and P17. *CMOS compatible input level. *N-channel open-drain output structure. *Interrupt input pin XCOUT XCIN Sub-clock output Sub-clock input *Sub-clock generating circuit I/O pins. (Connect a resonator. External clock cannot be used.) 5 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING Product M3827 7 M 8 M XXX HP Package type FP : 100P6S-A package HP : 100PFB-A package GP : 100P6Q-A package FS : 100D0 package ROM number Omitted in some types. Normally, using hyphen When electrical characteristic, or division of quality identification code using alphanumeric character. - : Standard M : Low power source version ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes Fig. 4 Part numbering 6 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION Mitsubishi plans to expand the 3827 group as follows: Package 100PFB-A ................................0.4 mm-pitch plastic molded TQFP 100P6Q-A ................................ 0.5 mm-pitch plastic molded LQFP 100P6S-A ................................ 0.65 mm-pitch plastic molded QFP 100D0 ..................... Window type ceramic LCC (EPROM version) Memory Type Support for Mask ROM, One Time PROM, and EPROM versions Memory Size ROM/PROM size ................................................. 4 K to 60 K bytes RAM size ............................................................ 192 to 2048 bytes Memory Expansion Plan ROM size (bytes) 60K 56K 52K Planning 48K 44K 40K 36K Under development 32K 28K 24K 20K 16K 12K 8K 4K 1408 M38277M8M M38278MCM Under development M38279EF 192 256 384 512 640 768 896 1024 1152 1280 1536 1664 1792 1920 2048 RAM size (bytes) Note: Products under development or planning: the development schedule and specifications may be revised without notice. Fig. 5 Memory expansion plan Currently supported products are listed below. Table 3 List of supported products Product M38277M8MXXXFP M38277M8MXXXHP M38277M8MXXXGP M38279EF-XXXFP M38279EFFP M38279EF-XXXHP M38279EFHP M38279EF-XXXGP M38279EFGP M38279EFFS (P) ROM size (bytes) ROM size for User in ( ) 32768 (32638) RAM size (bytes) Package 100P6S-A 100PFB-A 100P6Q-A 100P6S-A 100P6S-A 100PFB-A 100PFB-A 100P6Q-A 100P6Q-A 100D0 Remarks Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) One Time PROM version One Time PROM version (blank) One Time PROM version One Time PROM version (blank) EPROM version As of May 1998 1024 61440 (61310) 2048 7 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 3827 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the internal system clock selection bit. The CPU mode register is allocated at address 003B16. b7 b0 CPU mode register (CPUM (CM) : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Not used (returns "1" when read) (Do not write "0" to this bit.) Port XC switch bit 0 : Stop oscillating 1 : XCIN, XCOUT Main clock ( XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : XIN/2 (high-speed mode) 1 : XIN/8 (middle-speed mode) Internal system clock selection bit 0 : XIN-XOUT selected (middle-/high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode) Fig. 6 Structure of CPU mode register 8 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) 192 256 384 512 640 768 896 1024 1536 2048 Address XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 084016 Not used Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 FFFE16 Reserved ROM area FFFF16 Interrupt vector area FFDC16 Special page ROM FF0016 ZZZZ16 YYYY16 Reserved ROM area (128 bytes) XXXX16 Reserved area RAM 000016 SFR area 004016 005416 010016 LCD display RAM area Zero page ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Fig. 7 Memory map diagram 9 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 000216 Port P1 (P1) 000316 Port P1 output control register (P1D) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 Port P3 output control register (P3C) 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 Port P7 (P7) 000F16 Port P7 direction register (P7D) 001016 001116 001216 001316 001416 001516 Key input control register (KIC) 001616 PULL register A (PULLA) 001716 PULL register B (PULLB) 001816 Transmit/Receive buffer register(TB/RB) 001916 Serial I/O1 status register (SIO1STS) 001A16 Serial I/O1 control register (SIO1CON) 001B16 UART control register (UARTCON) 001C16 Baud rate generator (BRG) 001D16 Serial I/O2 control register (SIO2CON) 001E16 Reserved area 001F16 Serial I/O2 register (SIO2) 002016 Timer X (low) (TXL) 002116 Timer X (high) (TXH) 002216 Timer Y (low) (TYL) 002316 Timer Y (high) (TYH) 002416 Timer 1 (T1) 002516 Timer 2 (T2) 002616 Timer 3 (T3) 002716 Timer X mode register (TXM) 002816 Timer Y mode register (TYM) 002916 Timer 123 mode register (T123M) 002A16 TOUT/ output control register (CKCON) 002B16 PWM control register (PWMCON) 002C16 PWM prescaler (PREPWM) 002D16 PWM register (PWM) 002E16 002F16 003016 003116 A-D control register (ADCON) 003216 A-D control register (low-order) (ADL) 003316 A-D control register (high-order) (ADH) 003416 D-A1 conversion register (DA1) 003516 D-A2 conversion register (DA2) 003616 D-A control register (DACON) 003716 Watchdog timer control register (WDTCON) 003816 Segment output enable register (SEG) 003916 LCD mode register (LM) 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1(IREQ1) 003D16 Interrupt request register 2(IREQ2) 003E16 Interrupt control register 1(ICON1) 003F16 Interrupt control register 2(ICON2) Fig. 8 Memory map of special function register (SFR) 10 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS Direction Registers The I/O ports have direction registers which determine the input/ output direction of each individual pin. (P00-P07 and P10-P15 use bit 0 of port P0, P1 direction registers respectively.) When "1" is written to that bit, that pin becomes an output pin. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating and the value of that pin can be read. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. b7 b0 PULL register A (PULLA : address 001616) P00, P01 pull-up P02,P03 pull-up P04-P07 pull-up P10-P13 pull-up P14,P15 pull-up P16,P17 pull-up P20-P23 pull-up P24-P27 pull-up b7 b0 PULL register B (PULLB : address 001716) P41-P43 pull-up P44-P47 pull-up P50-P53 pull-up P54-P57 pull-up P60-P63 pull-up P64-P67 pull-up Not used (return "0" when read) 0 : No pull-up 1 : Pull-up Port P3 Output Control Register Bit 0 of the port P3 output control register (address 000716) enables control of the output of ports P30 to P37. When the bit is set to "1", the port output function is valid. When resetting, bit 0 of the port P3 output control register is set to "0" (the port output function is invalid.) and ports P30 to P37 are pulled up. Pull-up Control By setting the PULL register A (address 001616) or the PULL register B (address 001716), ports P0 to P6 can control pull-up with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports. The PULL register A setting is invalid for pins set to segment output on the segment output enable register. Note : The contents of PULL register A and PULL register B do not affect ports programmed as the output port. Fig. 9 Structure of PULL register A and PULL register B 11 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 4 List of I/O port function (1) Pin P00/SEG26- P07/SEG33 P10/SEG34- P15/SEG39 Name Por t P0 Input/Output Input/output, byte unit Input/output, 6-bit unit I/O Format CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS 3-state output Key input (key-on wake-up) interrupt input LCD segment output Non-Port Function LCD segment output Related SFRs PULL register A Segment output enable register PULL register A Segment output enable register PULL register A Diagram No. (1) (2) (1) (2) (4) Por t P1 LCD segment output P16 , P17 Input/output, individual bits P20-P27 Port P2 Input/output, individual bits PULL register A Interrupt control register2 Key input control register PULL register A Segment output enable register P3 output enable register A-D control register Interrupt edge selection register (4) P30/SEG18- P37/SEG25 Por t P3 Output (3) P40/ADT Por t P4 Input/output, individual bits CMOS compatible input level N-channel open-drain output CMOS compatible input level CMOS 3-state output A-D trigger input External interrupt input (13) P41/INT1, P42/INT2 P43//TOUT External interrupt input PULL register B Interrupt edge selection register PULL register B Timer 123 mode register TOUT/ output control register (4) Timer output output (12) P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/PWM0, P51/PWM1 P52/RTP0, P53/RTP1 P54/CNTR0 P55/CNTR1 P56/DA1 Port P5 Input/output, individual bits CMOS compatible input level CMOS 3-state output Serial I/O1 function I/O PULL register B Serial I/O1 control register Serial I/O1 status register UART control register PULL register B PWM control register PULL register B Timer X mode register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B D-A control register A-D control register PULL register B D-A control register (5) (6) (7) (8) (10) (9) (11) (14) (15) PWM output Real time port function output Timer X function I/O Timer Y function input DA1 output A-D VREF input P57/DA2 DA2 output (15) 12 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 5 List of I/O port function (2) Pin P60/SIN2/AN0 P61/SOUT2/ AN1 P62/SCLK21/ AN2 P63/SCLK22 / AN3 P64/AN4- P67/AN7 P70/INT0 P71-P77 Por t P7 Input Input/ output, individnal bits Common Segment Output Output CMOS compatible input level CMOS compatible input level N-channel open-drain output LCD common output LCD segment output LCD mode register A-D conversion input External interrupt input A-D control register Interrupt edge selection register Name Por t P6 Input/Output Input/ output, individnal bits I/O Format CMOS compatible input level CMOS 3-state output Non-Port Function A-D conversion input Serial I/O2 function I/O Related SFRS A-D control register Serial I/O2 control register Diagram No. (17) (18) (19) (20) (16) (23) (13) COM0-COM3 SEG0-SEG17 (21) (22) Notes1: How to use double-function ports as function I/O ports, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow VCC to VSS through the input-stage gate. 13 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Ports P01-P07, P11-P15 Pull-up LCD drive timing Segment data Data bus Port latch Port direction register VL2/VL3/VCC Segment/Port Interface logic level shift circuit Segment VL1/VSS Port Port/Segment Port direction register (2) Ports P00, P10 Pull-up LCD drive timing Direction register VL2/VL3/VCC Segment/Port Segment data Data bus Port latch Interface logic level shift circuit Segment VL1/VSS Port Port/Segment Port direction register (3) Port P3 Pull-up LCD drive timing Segment data Data bus Port latch Interface logic level shift circuit Port/Segment Output control VL2/VL3/VCC Segment/Port Segment VL1/VSS Port (4) Ports P16, P17, P2, P41, P42 Pull-up control (5) Port P44 Serial I/O1 enable bit Reception enable bit Direction register Pull-up control Direction register Data bus Port latch Data bus Port latch Key input interrupt input INT1, INT2 interrupt input Except P16, P17 Serial I/O1 input Fig. 10 Port block diagram (1) 14 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (6) Port P45 Pull-up control P45/TxD P-channel output disable bit Serial I/O1 enable bit Transmission enable bit Direction register (7) Port P46 Serial I/O1 clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Pull-up control Data bus Port latch Data bus Port latch Serial I/O1 output Serial I/O1 clock outupt Serial I/O1 clock input (8) Port P47 Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register (9) Ports P52, P53 Pull-up control Pull-up control Direction register Data bus Port latch Data bus Port latch Serial I/O1 ready output Real time control bit Real time port data (10) Ports P50,P51 Pull-up control (11) Port P54 Pull-up control Direction register Direction register Data bus Data bus Port latch Port latch Pulse output mode Timer output PWM function enable bit PWM output CNTR0 interrupt input Fig. 11 Port block diagram (2) 15 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (12) Port P43 Pull-up control (13) Ports P40, P71-P77 Direction register Direction register Data bus Port latch Data bus Port latch TOUT/ output control Timer output TOUT/ selection bit output A-D trigger input Except P71 to P77 (14) Port P55 (15) Ports P56, P57 Pull-up control Pull-up control Direction register Direction register Data bus Port latch Data bus Port latch CNTR1 interrupt input Except P57 D-A conversion output D-A1, D-A2 output enable bit VREF input switch VREF input selection bit (16) Ports P64-P67 Pull-up control (17) Port P60 Pull-up control Direction register Direction register Data bus Port latch Data bus Port latch A-D conversion input Analog input pin selection bit Serial I/O2 input A-D conversion input Analog input pin selection bit Fig. 12 Port block diagram (3) 16 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (18) Port P61 P61/SOUT2 P-channel output disable bit Serial I/O2 transmit completion signal Synchronous clock selection bit Serial I/O2 port selection bit Direction register (19) Port P62 Pull-up control Synchronous clock selection bit Serial I/O2 port selection bit Synchronous clock output pin selection bit Direction register Pull-up control Data bus Port latch Data bus Port latch Serial I/O2 output A-D conversion input Analog input pin selection bit Serial I/O2 clock output Serial I/O2 clock input A-D conversion input Analog input pin selection bit (20) Port P63 Pull-up control Synchronous clock selection bit Serial I/O2 port selection bit Synchronous clock output pin selection bit Direction register (21) COM0-COM3 VL3 Data bus VL2 Port latch VL1 The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. Serial I/O2 clock output A-D conversion input Analog input pin selection bit VSS (22) SEG0-SEG17 VL2/VL3 The voltage applied to the sources of P-channel and N-channel transistors is the controlled voltage by the bias value. VL1/VSS (23) Port P70 Direction register Data bus Port latch INT0 input Fig. 13 Port block diagram (4) 17 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS Interrupts occur by seventeen sources: seven external, nine internal, and one software. Interrupt Operation Upon acceptance of an interrupt the following operations are automatically performed: 1. The contents of the program counter and processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. Interrupt Control Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0." Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first. sNotes When the active edge of an external interrupt (INT0-INT2, CNTR0, CNTR1) is set or when switching interrupt sources of ADT/A-D conversion interrupt, the corresponding interrupt request bit may also be set. Therefore, take following sequence: (1) Disable the external interrupt which is selected. (2) Change the active edge in interrupt edge selection register (timer XY mode register when using CNTR0, CNTR1) (3) Clear the set interrupt request bit to "0." (4) Enable the external interrupt which is selected. Table 6 Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 INT1 Serial I/O1 reception Serial I/O1 transmission Timer X Timer Y Timer 2 Timer 3 CNTR0 CNTR1 Timer 1 INT2 Serial I/O2 Key input (Key-on wake-up) ADT Priority 1 2 3 4 5 Vector Addresses (Note 1) High Low FFFD16 FFFB16 FFF916 FFF716 FFF516 FFFC16 FFFA16 FFF816 FFF616 FFF416 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmit shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At detection of either rising or falling edge of INT2 input At completion of serial I/O2 data transmission or reception At falling of conjunction of input level for port P2 (at input mode) At falling of ADT input External interrupt (active edge selectable) Valid when serial I/O2 is selected External interrupt (valid when an "L" level is applied) Valid when ADT interrupt is selected External interrupt (Valid at falling) Valid when A-D interrupt is selected Non-maskable software interrupt Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected 6 7 8 9 10 11 12 13 14 15 16 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 External interrupt (active edge selectable) External interrupt (active edge selectable) A-D conversion BRK instruction 17 FFDD16 FFDC16 At completion of A-D conversion At BRK instruction execution Notes1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 18 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 14 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active Not used (return "0" when read) b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1 interrupt request bit Timer 1 interrupt request bit INT2 interrupt request bit Serial I/O2 interrupt request bit Key input interrupt request bit ADT/AD conversion interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit b7 b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit Serial I/O2 interrupt enable bit Key input interrupt enable bit ADT/AD conversion interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit.) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 15 Structure of interrupt-related registers 19 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Key Input Interrupt (Key-on wake-up) A Key-on wake up interrupt request is generated by applying "L" level to any pin of port P2 that have been set to input mode. In other words, it is generated when AND of input level goes from "1" to "0". An example of using a key input interrupt is shown in Figure 16, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20-P23. Port PXx "L" level output PULLA register Key input control register = "1" Bit 2 = "1" Port P27 direction register = "1" VV Port P27 latch Key input interrupt request V Port P27 output V Port P26 output Key input control register = "1" Port P26 direction register = "1" VV Port P26 latch V Port P25 output Key input control register = "1" Port P25 direction register = "1" VV Port P25 latch V Port P24 output Key input control register = "1" Port P24 direction register = "1" VV Port P24 latch V Port P23 input Key input control register = "1" Port P23 direction register = "0" VV Port P23 latch Port P2 input reading circuit V Port P22 input Key input control register = "1" Port P22 direction register = "0" VV Port P22 latch V Port P21 input Key input control register = "1" Port P21 direction register = "0" VV Port P21 latch V Port P20 input Key input control register = "1" Port P20 direction register = "0" VV Port P20 latch V P-channel transistor for pull-up VV CMOS output buffer Fig. 16 Connection example when using key input interrupt and port P2 block diagram 20 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMERS The 3827 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches "0016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit cor- responding to that timer is set to "1". Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. Real time port control bit "1" QD P52 P52 direction register Latch "0" P52 latch Real time port control bit "1" QD "0" P53 latch f(XIN)/16 (f(XIN)/16 in low-speed mode V ) CNTR0 active edge switch bit "0" Timer X operating mode bits "00","01","11" Data bus P52 data for real time port P53 P53 direction register Latch P53 data for real time port Real time port control bit "0" "1" Timer X stop control bit Timer X (low) latch (8) Timer X (low) (8) Timer X mode register write signal Timer X write control bit Timer X (high) latch (8) Timer X (high) (8) P54/CNTR0 "10" "1" Pulse width measurement mode CNTR0 active edge switch bit "0" "1" P54 direction register P54 latch Pulse output mode Timer X interrupt request CNTR0 interrupt request Pulse output mode QS T Q Rising edge detection Timer Y operating mode bit "00","01","10" Pulse width HL continuously measurement mode CNTR1 interrupt request "11" Period measurement mode Falling edge detection f(XIN)/16 (f(XCIN)!16 in = XCIN divided by 2) P55/CNTR1 CNTR1 active edge switch bit "0" "1" Timer Y stop control bit "00","01","11" Timer Y (low) latch (8) Timer Y (low) (8) Timer Y (high) latch (8) Timer Y (high) (8) "10" Timer Y operating mode bit Timer Y interrupt request f(XIN)/16 (f(XCIN)/16 in = XCIN divided by 2) Timer 1 count source selection bit "0" Timer 1 latch (8) XCIN "1" Timer 1 (8) Timer 2 count source selection bit Timer 2 latch (8) "0" Timer 2 (8) "1" f(XIN)/16 (f(XCIN)!16 in =XCIN divided by 2) Timer 2 write control bit Timer 1 interrupt request Timer 2 interrupt request TOUT output TOUT output active edge control bit TOUT output switch bit control bit "0" QS P43//TOUT T "1" P43 latch Q P43 direction register f(XIN)/16(f(XCIN)/16 in low-speed mode V) "0" Timer 3 latch (8) Timer 3 (8) "1" Timer 3 count source selection bit Timer 3 interrupt request Fig. 17 Timer block diagram 21 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer X Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. sNote on CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. qReal time port control While the real time port function is valid, data for the real time port are output from ports P52 and P53 each time the timer X underflows. (However, if the real time port control bit is changed from "0" to "1", data are output without the timer X.) When the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode. (1) Timer Mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Pulse Output Mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR0 pin to input. (3) Event Counter Mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR0 pin to input. b7 b0 Timer X mode register (TXM : address 002716) Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid P52 data for real time port P53 data for real time port Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Count at rising edge in event counter mode Start from "H" output in pulse output mode Measure "H" pulse width in pulse width measurement mode Falling edge active for CNTR0 interrupt 1 : Count at falling edge in event counter mode Start from "L" output in pulse output mode Measure "L" pulse width in pulse width measurement mode Rising edge active for CNTR0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop (4) Pulse Width Measurement Mode The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If CNTR0 active edge switch bit is "0", the timer counts while the input signal of CNTR0 pin is at "H". If it is "1", the timer counts while the input signal of CNTR0 pin is at "L". When using a timer in this mode, set the port shared with tha CNTR0 pin to input. qTimer X write control If the timer X write control bit is "0", when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is "1", when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. Fig. 18 Structure of timer X mode register 22 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer Y Timer Y is a 16-bit timer that can be selected in one of four modes. b7 b0 Timer Y mode register (TYM : address 002816) Not used (return "0" when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop (1) Timer Mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Period Measurement Mode CNTR1 interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR1 pin input signal is found by CNTR1 interrupt. When using a timer in this mode, set the por t shared with the CNTR1 pin to input. (3) Event Counter Mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR1 pin to input. Fig. 19 Structure of timer Y mode register (4) Pulse Width HL Continuously Measurement Mode CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the port shared with the CNTR1 pin to input. sNote on CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. 23 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. However, because changing the count source may cause an inadvertent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed. qTimer 2 write control If the timer 2 write control bit is "0", when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is "1", when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. qTimer 2 output control When the timer 2 (TOUT) is output enabled, an inversion signal from the TOUT pin is output each time timer 2 underflows. In this case, set the port shared with the TOUT pin to the output. b7 b0 Timer 123 mode register (T123M :address 002916) TOUT output active edge switch bit 0 : Start at "H" output 1 : Start at "L" output TOUT/ output control bit 0 : TOUT/ output disabled 1 : TOUT/ output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 1 : f(XCIN) Not used (return "0" when read) Note : Internal clock is XCIN/2 in the low-speed mode. sNotes on timer 1 to timer 3 When the count source of timer 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is generated in count input of timer . If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 20 Structure of timer 123 mode register 24 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 can be selected by setting the mode selection bit of the serial I/O1 control register to "1". For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer registers. Data bus Address 001816 Receive buffer register Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit P44/RXD Receive shift register Shift clock P46/SCLK BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P47/SRDY1 F/F Falling-edge detector Serial I/O1 clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1/4 Address 001C16 Clock control circuit Shift clock P45/TXD Transmit shift register Transmit buffer register Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Address 001916 Address 001816 Data bus Serial I/O1 status register Fig. 21 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TXD Serial input RXD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY1 Write signal to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 22 Operation of clock synchronous serial I/O1 function 25 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O1 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 001816 Receive buffer register OE Character length selection bit 7 bits STdetector Receive shift register 8 bits Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 P44/RXD PE FE SP detector Clock control circuit UART control register Address 001B16 Serial I/O synchronous clock selection bit P46/SCLK BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 ST/SP/PA generator 1/16 P45/TXD Character length selection bit Transmit buffer register Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 001916 Transmit shift register Address 001816 Data bus Fig. 23 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD ST D0 TBE=0 TBE=1 D1 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 VGenerated TSC=1 V SP at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=1 Serial input RXD ST D0 D1 SP ST D0 RBF=0 RBF=1 D1 SP Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1" by the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes "1". 4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 24 Operation of UART serial I/O1 function 26 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Transmit Buffer/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is write-only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is "0". [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE. Writing "0" to the serial I/O1 enable bit (SIOE) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register contains eight control bits for the serial I/O1 function. [UART Control Register (UARTCON) ]001B16 This is a 5 bit register containing four control bits, which are valid when UART is selected and set the data format of an data receiver/transfer, and one control bit, which is always valid and sets the output structure of the P45/TXD pin. [Baud Rate Generator(BRG)] 001616 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. 27 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O1 status register (SIO1STS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: OE U PE U FE =0 1: OE U PE U FE =1 Not used (returns "1" when read) b7 b0 Serial I/O1 control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin. 1: P47 pin operates as SRDY1 output pin. Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44-P47 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P44-P47 operate as serial I/O pins) b7 b0 UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return "1" when read) Fig. 25 Structure of serial I/O1 control registers 28 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2 the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register. When an internal clock is selected as the synchronous clock of the serial I/O2, either P62 or P63 can be selected as an output pin of the synchronous clock. In this case, the pin that is not selected as an output pin of the synchronous clock functions as a port. b7 b0 Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock select bits b2 b1 b0 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 0 0: 1 0 1: Do not set 1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK21/SCLK22 signal output P61/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Transfer direction selection bit 0: LSB first 1: MSB first Synchronous clock selection bit 0: External clock 1: Internal clock Synchronous clock output pin selection bit 0: SCLK21 1: SCLK22 [Serial I/O2 Control Register (SIO2CON)] 001D16 The serial I/O2 control register contains 8 bits which control various serial I/O2 functions. Fig. 26 Structure of serial I/O2 control register 1/8 1/16 Internal synchronous clock select bits f(XIN) (f(XCIN) in low-speed mode) Divider 1/32 1/64 1/128 1/256 Data bus P63 latch (Note) Synchronous clock selection bit Synchronous circuit "1" P63/SCLK22 SCLK2 "0" External clock P62 latch "0" P62/SCLK21 (Note) "1" P61 latch "0" Serial I/O counter 2 (3) Serial I/O2 interrupt request P61/SOUT2 "1" Serial I/O2 port selection bit P60/SIN2 Serial I/O shift register 2 (8) Note: It is selected by the synchronous clock selection bit, the synchronous clock output pin selection bit, and the serial I/O port selection bit. Fig. 27 Block diagram of serial I/O2 function 29 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Transfer clock (Note 1) Serial I/O2 register write signal (Note 2) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the S OUT2 pin goes to high impedance after transfer completion. When the external clock is selected as the transfer clock, a content of the serial I/O shift register is continued to shift during inputting a transfer clock. The SOUT2 pin does not go to high impedance after transfer completion. Fig. 28 Timing of serial I/O2 function 30 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PULSE WIDTH MODULATION (PWM) The 3827 group has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2. PWM Operation When at least either bit 1 (PWM0 output enable bit) or bit 2 (PWM1 output enable bit) of the PWM control register is set to "1", operation starts by initializing the PWM output circuit, and pulses are output starting at an "H". When one PWM output is enabled and that the other PWM output is enabled, PWM output which is enabled to output later starts pulse output from halfway. When the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Data Setting The PWM output pin also functions as ports P50 and P51. Set the PWM period by the PWM prescaler, and set the period during which the output pulse is an "H" by the PWM register. If PWM count source is f(XIN) and the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ! (n+1)/f(XIN) = 51 ! (n+1) s (when XIN = 5 MHz) Output pulse "H" period = PWM period ! m/255 = 0.2 ! (n+1) ! m s (when XIN = 5 MHz) 51 ! m ! (n+1) 255 s PWM output T = [51 ! (n+1)] s m: Contents of PWM register n : Contents of PWM prescaler T : PWM cycle (when f(XIN) = 5 MHz) Fig. 29 Timing of PWM cycle Data bus PWM prescaler pre-latch PWM register pre-latch PWM1 enable bit Transfer control circuit PWM prescaler latch Count source selection bit "0" XIN "1" PWM prescaler PWM register latch Port P56 PWM circuit 1/2 PWM0 enable bit Fig. 30 Block diagram of PWM function 31 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 PWM control register (PWMCON : address 002B16) Count source selection bit 0 : f(XIN) 1 : f(XIN)/2 PWM0 function enable bit 0 : PWM0 disabled 1 : PWM0 enabled PWM1 function enable bit 0 : PWM1 disabled 1 : PWM1 enabled Not used (return "0" when read) Fig. 31 Structure of PWM control register A B C B=C T2 T PWM (internal) stop T T T2 stop PWM0 output Port Port PWM1 output Port Port PWM register write signal (Changes from "A" to "B" during "H" period) PWM prescaler write signal (Changes from "T" to "T2" during PWM period) PWM0 function enable bit PWM1 function enable bit When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig. 32 PWM output timing when PWM register or PWM prescaler is changed 32 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER [A-D Conversion Register (AD)] 003516 The A-D conversion register is a read-only register that contains the result of an A-D conversion. During A-D conversion, do not read this register. b7 b0 A-D control register (ADCON : address 003116) Analog input pin selection bits 0 0 0 : P60/SIN2/AN0 0 0 1 : P61/SOUT2/AN1 0 1 0 : P62/SCLK21/AN2 0 1 1 : P63/SCLK22/AN3 1 0 0 : P64/AN4 1 0 1 : P65/AN5 1 1 0 : P66/AN6 1 1 1 : P67/AN7 AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed VREF input switch bit 0 : OFF 1 : ON AD external trigger valid bit 0 : A-D external trigger invalid 1 : A-D external trigger valid Interrupt source selection bit 0 : Interrupt request at A-D conversion completed 1 : Interrupt request at ADT input rising or falling Reference voltage input selection bit 0 : VREF 1 : P56/DA1 [A-D Control Register (ADCON)] 003416 The A-D control register controls the A-D conversion process. Bits 0 to 2 are analog input pin selection bits. Bit 3 is an A-D conversion completion bit and "0" during A-D conversion, then changes to "1" when the A-D conversion is completed. Writing "0" to this bit starts the A-D conversion. Bit 4 controls the transistor which breaks the through current of the resistor ladder. When bit 5, which is the AD external trigger valid bit, is set to "1", A-D conversion is started even by a rising edge or falling edge of an ADT input. Set ports which share with ADT pins to input when using an A-D external trigger. [Comparison Voltage Generator] The comparison voltage generator divides the voltage between AVSS and VREF, and outputs the divided voltages. [Channel Selector] The channel selector selects one of the input ports P67/AN7-P60/ AN0, and inputs it to the comparator. 8-bit read (Read only address 003216.) b7 (Address 003216) b0 b9 b8 b7 b6 b5 b4 b3 b2 [Comparator and Control Circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Note that the comparator is constructed linked to a capacitor, so set f(XIN) to at least 500 kHz during A-D conversion. Use a clock divided the main clock XIN as the internal clock . 10-bit read (Read address 003316 first.) b7 (Address 003316) b7 (Address 003216) b0 b9 b8 b0 b7 b6 b5 b4 b3 b2 b1 b0 Note: High-order 6 bits of address 003316 becomes "0" at reading. Fig. 33 Structure of A-D control register Data bus b7 A-D control register P40/ADT 3 b0 P60/SIN2/AN0 Channel selector P61/SOUT2/AN1 P62/SCLK21/AN2 P63/SCLK22/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 A-D control register (H) Comparater A-D conversion register ADT/A-D interrupt request (L) A-D conversion register 10 Resistor ladder AVSS VREF P56/DA1 Fig. 34 A-D converter block diagram 33 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D-A CONVERTER The 3827 group has an on-chip D-A converter with 8-bit resolution and 2 channels (DAi (i=1, 2)). The D-A converter is performed by setting the value in the D-A conversion register. The result of D-A converter is output from DAi pin. When using the D-A converter, the corresponding port direction register bit (P56/DA1, P57/DA2) should be set to "0" (input status). The output analog voltage V is determined by the value n (base 10) in the D-A conversion register as follows: V=VREF ! n/256 (n=0 to 255) Where VREF is the reference voltage. At reset, the D-A conversion registers are cleared to "0016", the DAi output enable bits are cleared to "0", and DAi pin goes to high impedance state. The DA output is not buffered, so connect an external buffer when driving a low-impedance load. b7 b0 D-A control register (DACON : address 0036 16) DA1 output enable bit/DA 1 VREF ON/OFF switch DA2 output enable bit/DA 2 VREF ON/OFF switch Not used (return "0" when read) 0 : Output disabled/OFF 1 : Output enabled/ON Fig. 35 Structure of D-A control register Data bus D-A1 conversion register (0034 16) D-A2 conversion register (0035 16) D-A i conversion register (8) DA i output enable bit R-2R resistor ladder P56/DA1 P57/DA2 Fig. 36 Block diagram of D-A converter VREF Internal: D-A output External: VREF Reference voltage input select switch Resistor ladder VREF input ON/OFF switch A-D conversion register (10 bits) D-A1 output (P56) D-A1 output enable switch D-A1 VREF ON/OFF switch R-2R resistor ladder D-A1 conversion register (8 bits) D-A2 output enable switch D-A2 VREF ON/OFF switch D-A2 output R-2R resistor ladder (P57) D-A2 conversion register (8 bits) Fig. 37 A-D converter, D-A converter block diagram 34 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCD DRIVE CONTROL CIRCUIT The 3827 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. qLCD display RAM qSegment output enable register qLCD mode register qVoltage multiplier qSelector qTiming controller qCommon driver qSegment driver qBias control circuit A maximum of 40 segment output pins and 4 common output pins can be used. Up to 160 pixels can be controlled for LCD display. When the LCD enable bit is set to "1" after data is set in the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. Table 7 Maximum number of display pixels at each duty ratio Duty ratio 2 3 4 Maximum number of display pixel 80 dots or 8 segment LCD 10 digits 120 dots or 8 segment LCD 15 digits 160 dots or 8 segment LCD 20 digits b7 b0 Segment output enable register (SEG : address 003816) Segment output enable bit 0 0 : Output ports P30-P35 1 : Segment output SEG18-SEG23 Segment output enable bit 1 0 : Output ports P36, P37 1 : Segment output SEG24,SEG25 Segment output enable bit 2 0 : I/O ports P00-P05 1 : Segment output SEG26-SEG31 Segment output enable bit 3 0 : I/O ports P06,P07 1 : Segment output SEG32,SEG33 Segment output enable bit 4 0 : I/O port P10 1 : Segment output SEG34 Segment output enable bit 5 0 : I/O ports P11-P15 1 : Segment output SEG35-SEG39 LCD output enable bit 0 : Disable 1 : Enable Not used (return "0" when read) (Do not write "1" to this bit) b7 b0 LCD mode register (LM : address 003916) Duty ratio selection bits 0 0 : Not used 0 1 : 2 duty (use COM0, COM1) 1 0 : 3 duty (use COM0-COM2) 1 1 : 4 duty (use COM0-COM3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON Voltage multiplier control bit 0 : Voltage multiplier disabled 1 : Voltage multiplier enabled LCD circuit divider division ratio selection bits 0 0 : 1 division of clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input LCDCK count source selection bit (Note) 0 : f(XCIN)/32 1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode) Note : LCDCK is a clock for a LCD timing controller. Fig. 38 Structure of LCD mode register 35 36 LCD enable bit Address 005316 LCD display RAM LCD circuit divider division ratio selection bits 2 Voltage multiplier control bit Bias control bit LCD divider 2 Duty ratio selection bits LCDCK count source selection bit "0" f(XCIN)/32 "1" f(XIN)/8192 (f(XCIN)/8192 in low-speed mode) Selector Selector Timing controller LCDCK Level shift Bias control VCC Level shift Level Shift Level Shift Level Shift Level Shift LCD output enable bit Segment Segment driver driver Common driver Common driver Common driver Common driver Data bus Fig. 39 Block diagram of LCD controller/driver Address 004016 Address 004116 Selector Selector Selector Selector Level shift Level shift Level shift Level shift Segment Segment Segment Segment driver driver driver driver 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS SEG0 P14/SEG38 P15/SEG39 SEG1 SEG2 SEG3 P30/SEG18 VSS VL1 VL2 VL3 C1 C2 COM0 COM1 COM2 COM3 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE MULTIPLIER (3 TIMES) The voltage multiplier performs threefold boosting. This circuit inputs a reference voltage for boosting from LCD power input pin VL1. (However, when using a 1/2 bias, connect VL1 and VL2 and apply voltage by external resistor division.) Set each bit of the segment output enable register and the LCD mode register in the following order for operating the voltage multiplier. 1. Set the segment output enable bits (bits 0 to 5) of the segment output enable register to "0" or "1." 2. Set the duty ratio selection bits (bits 0 and 1), the bias control bit (bit 2), the LCD circuit divider division ratio selection bits (bits 5 and 6), and the LCDCK count source selection bit (bit 7) of the LCD mode register to "0" or "1." 3. Set the LCD output enable bit (bit 6) of the segment output enable register to "1." 4. Set the voltage multiplier control bit (bit 4) of the LCD mode register to "1." When voltage is input to the VL1 pin during operating the voltage multiplier, voltage that is twice as large as VL1 occurs at the VL2 pin, and voltage that is three times as large as VL1 occurs at the VL3 pin. When using the voltage multiplier, apply 1.3 V Voltage 2.3 V to the VL1 pin. When not using the voltage multiplier,apply proper voltage to the LCD power input pins (VL1-VL3). Then set the LCD output enable bit to "1." When the LCD output enable bit is set to "0," the VCC voltage is applied to the VL3 pin inside of this microcomputer. The voltage multiplier control bit (bit 4 of the LCD mode register) controls the voltage multiplier. Bias Control and Applied Voltage to LCD Power Input Pins To the LCD power input pins (VL1-VL3), apply the voltage shown in Table 8 according to the bias value. Select a bias value by the bias control bit (bit 2 of the LCD mode register). Table 8 Bias control and applied voltage to VL1-VL3 Bias value 1/3 bias VL3=VLCD VL2=2/3 VLCD VL1=1/3 VLCD VL3=VLCD VL2=VL1=1/2 VLCD Voltage value 1/2 bias Note 1: V LCD is the maximum value of supplied voltage for the LCD panel. Contrast control VCC VL3 VL2 C2 C1 VL1 VL3 R1 VL2 C2 C1 VL1 R3 PXX R1=R2=R3 1/3 bias when using the voltage multiplier 1/3 bias when not using the voltage multiplier 1/2 bias Open R2 Open C1 VL1 Open VL2 C2 Open VCC VL3 Contrast control R4 R5 R4=R5 Fig. 40 Example of circuit at each bias 37 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Common Pin and Duty Ratio Control The common pins (COM0-COM3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). When releasing from reset, the VCC (VL3) voltage is output from the common pins. Table 9 Duty ratio control and common pins used Duty ratio 2 3 4 Duty ratio selection bit Bit 1 0 1 1 Bit 0 1 0 1 Common pins used COM0, COM1 (Note 1) COM0-COM2 (Note 2) COM0-COM3 ment/output port pins are pulled up to the VCC (=VL3) voltage in the high impedance condition. The segment/I/O port pins are set to input ports, and VCC (=VL3) is applied to them by pull-up resistor. LCD Display RAM Address 004016 to 005316 is the designated RAM for the LCD display. When "1" are written to these addresses, the corresponding segments of the LCD display panel are turned on. LCD Drive Timing The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation; f(LCDCK) = (frequency of count source for LCDCK) (divider division ratio for LCD) f(LCDCK) (duty ratio) Notes1: COM2 and COM3 are open. 2: COM3 is open. Segment Signal Output Pin Segment signal output pins are classified into the segment-only pins (SEG0-SEG17), the segment/output port pins (SEG18- SEG25), and the segment/I/O port pins (SEG26-SEG39). Segment signals are output according to the bit data of the LCD RAM corresponding to the duty ratio. After reset release, a VCC (=VL3) voltage is output to the segment-only pins and the seg- Frame frequency = Bit 7 address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17 SEG19 SEG21 SEG23 SEG25 SEG27 SEG29 SEG31 SEG33 SEG35 SEG37 SEG39 SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22 SEG24 SEG26 SEG28 SEG30 SEG32 SEG34 SEG36 SEG38 6 5 4 3 2 1 0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 Fig. 41 LCD display RAM map 38 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Internal signal LCDCK timing 1/4 duty Voltage level VL3 VL2=VL1 VSS COM0 COM1 COM2 COM3 SEG0 VL3 VSS OFF COM3 COM2 COM1 ON COM0 COM3 OFF COM2 COM1 ON COM0 1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2=VL1 VSS SEG0 ON COM0 1/2 duty COM0 COM1 SEG0 OFF COM2 ON COM1 COM0 OFF COM2 ON COM1 COM0 OFF COM2 VL3 VL2=VL1 VSS VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 Fig. 42 LCD drive waveform (1/2 bias) 39 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Internal signal LCDCK timing 1/4 duty Voltage level COM0 VL3 VL2 VL1 VSS COM1 COM2 COM3 SEG0 VL3 VSS OFF COM3 COM2 COM1 ON COM0 COM3 OFF COM2 COM1 ON COM0 1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2 VL1 VSS SEG0 ON COM0 1/2 duty COM0 COM1 SEG0 OFF COM2 ON COM1 COM0 OFF COM2 ON COM1 COM0 OFF COM2 VL3 VL2 VL1 VSS VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 Fig. 43 LCD drive waveform (1/3 bias) 40 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software runaway). The watchdog timer consists of an 8-bit watchdog timer L and a 6bit watchdog timer H. At reset or writing to the watchdog timer control register (address 003716), the watchdog timer is set to "3FFF16." When any data is not written to the watchdog timer control register (address 003716) after reset, the watchdog timer is in stop state. The watchdog timer starts to count down from "3FFF16" by writing an optional value into the watchdog timer control register (address 003716) and an internal reset occurs at an underflow. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 003716) may be started before an underflow. The watchdog timer does not function when an optional value have not written to the watchdog timer control register (address 003716). When address 003716 is read, the following values are read: qvalue of high-order 6-bit counter qvalue of STP instruction disable bit qvalue of count source selection bit. When bit 6 of the watchdog timer control register (address 003716) is set to "0," the STP instruction is valid. The STP instruction is disabled by rewriting this bit to "1." At this time, if the STP instruction is executed, it is processed as an undefined instruction, so that a reset occurs inside. This bit cannot be rewritten to "0" by programming. This bit is "0" immediately after reset. The count source of the watchdog timer becomes the system clock divided by 8. The detection time in this case is set to 8.19 s at XCIN = 32 kHz and 65.536 ms at XIN = 4 MHz. However, count source of high-order 6-bit timer can be connected to a signal divided system clock by 8 directly by writing the bit 7 of the watchdog timer control register (address 003716) to "1." The detection time in this case is set to 32 ms at XCIN = 32 kHz and 256 s at XIN = 4 MHz. There is no difference in the detection time between the middle-speed mode and the high-speed mode. XCIN "1" Internal system clock selection bit "0" XIN "FF16" is set when watchdog timer is written to. Watchdog timer L (8) Data bus Watchdog timer count source selection bit "0" "1" Watchdog timer H (6) 1/16 Undefined instruction Reset STP instruction disable bit STP instruction RESETIN "3F16" is set when watchdog timer is written to. Internal reset Reset circuit Reset release time wait Fig. 44 Block diagram of watchdog timer b7 b0 Watchdog timer register (address 003716) WDTCON Watchdog timer H (for read-out of high-order 6 bit) "3FFF16" is set to the watchdog timer by writing values to this address. STP instruction disable bit 0 STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selection bit 0 : Internal system clock/2048 (f(XIN)/4096) 1 : Internal system clock/8 (f(XIN)/16) Fig. 45 Structure of watchdog timer control register f(XIN) Internal reset signal Watchdog timer detection 2ms (f(XIN) = 4MHZ) Fig. 46 Timing of reset output 41 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TOUT/ CLOCK OUTPUT FUNCTION The internal system clock or timer 2 divided by 2 (TOUT output) can be output from port P43 by setting the TOUT/ output control bit (bit 1) of the timer 123 mode register and the TOUT/ output control register. Set bit 3 of the port P4 direction register to "1" when outputting the clock. b7 b0 TOUT/ output control register (CKOUT : address 002A16) TOUT/ output control bit 0 : clock output 1 : TOUT output Not used (return "0" when read) b7 b0 Timer 123 mode register (T123M : address 002916) TOUT output active edge switch bit 0 : Start on "H" output 1 : Start on "L" output TOUT/ output control bit 0 : TOUT/ output disable 1 : TOUT/ output enable Timer 2 write control bit 0 : Write data in latch and timer 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode V) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode V) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode V) 1 : f(XCIN) Not used (return "0" when read) V : Internal clock is f(XCIN)/2 in low-speed mode. Fig. 47 Structure of TOUT/ output-related register 42 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between VCC(min.) and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.2 VCC for VCC of VCC (min.). Poweron Power source voltage 0V Reset input voltage 0V (Note) RESET VCC 0.2VCC Note : Reset release voltage ; VCC=VCC(min.) RESET VCC Power source voltage detection circuit Fig. 48 Reset Circuit Example XIN RESET Internal reset Reset address from vector table Address Data ? ? ? ? FFFC ADL FFFD ADH, ADL ADH SYNC XIN : about 8200 cycles Notes 1: The frequency relation of f(XIN) and f() is f(XIN) = 8 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 49 Reset Sequence 43 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 output control register (5) Port P4 direction register (6) Port P5 direction register (7) Port P6 direction register (8) Port P7 direction register (9) Key input control register (10) PULL register A (11) PULL register B (12) Serial I/O1 status register (13) Serial I/O1 control register (14) UART control register (15) Serial I/O2 control register (16) Timer X (low-order) (17) Timer X (high-order) (18) Timer Y (low-order) (19) Timer Y (high-order) (20) Timer 1 (21) Timer 2 (22) Timer 3 (23) Timer X mode register (24) Timer Y mode register (25) Timer 123 mode register (26) TOUT/ output control register (27) PWM control register 000116 000316 000516 000716 000916 000B16 000D16 000F16 001516 001616 001716 Register contents 0016 0016 0016 0016 0016 0016 0016 0016 0016 3F16 0016 (28) A-D control register (29) A-D conversion register (low-order) (30) A-D conversion register (high-order) (31) D-A1 conversion register (32) D-A2 conversion register (33) D-A control register Address 003116 003216 003316 003416 003516 003616 Register contents 0816 XX16 XX16 0016 0016 0016 00111111 0016 0016 0016 01001000 0016 0016 0016 0016 (34) Watchdog timer control register 003716 (35) Segment output enable register 003816 (36) LCD mode register 003916 (37) Interrupt edge selection register 003A16 (38) CPU mode register (39) Interrupt request register 1 (40) Interrupt request register 2 (41) Interrupt control register 1 (42) Interrupt control register 2 (43) Processor status register (44) Program counter 003B16 003C16 003D16 003E16 003F16 001916 1 0 0 0 0 0 0 0 001A16 0016 001B16 1 1 1 0 0 0 0 0 001D16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 0016 FF16 FF16 FF16 FF16 FF16 0116 FF16 0016 0016 0016 0016 0016 (PS) ! ! ! ! ! 1 ! ! (PCH) (PCL) Contents of address FFFD 16 Contents of address FFFC 16 (45) Watchdog timer (high-order) (46) Watchdog timer (low-order) 3F16 FF16 Note: The contents of all other register and RAM are undefined after reset, so they must be initialized by software. ! : Undefined Fig. 50 Initial status at reset 44 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The 3827 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external resonator to oscillate. Immediately after poweron, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins go to high impedance state. Oscillation Control (1) Stop Mode If the STP instruction is executed, the internal clock stops at an "H" level, and XIN and XCIN oscillators stop. The value set to the timer latch 1 and the timer latch 2 is loaded automatically to the timer 1 and the timer 2. Thus, a value generated time for stabilizing oscillation should be set to the timer 1 latch and the timer 2 latch (low-order 8 bits for the timer 1, high-order 8 bits for the timer 2) before executing the STP instruction. Either XIN or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are cleared to "0," Set the timer 1 and timer 2 interrupt enable bits to disabled ("0") before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock is not supplied to the CPU until timer 2 underflows..This allows timer for the clock circuit oscillation to stabilize. Frequency Control (1) Middle-speed Mode The internal clock is the frequency of XIN divided by 8. After reset, this mode is selected. (2) Wait Mode If the WIT instruction is executed, the internal clock stops at an "H" level. The states of XIN and XCIN are the same as the state before the executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restar ted. (2) High-speed Mode The internal clock is half the frequency of XIN. (3) Low-speed Mode qThe internal clock is half the frequency of XCIN. qA low-power consumption operation can be realized by stopping the main clock XIN in this mode. To stop the main clock, set bit 5 of the CPU mode register to "1". When the main clock XIN is restarted, set enough time for oscillation to stabilize by programming. Note: If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after poweron and at returning from stop mode. When switching the mode between middle/highspeed and low-speed, set the frequency on condition that f(XIN)>3f(XCIN). XCIN Rf CCIN XCOUT Rd CCOUT XIN XOUT CIN COUT Fig. 51 Ceramic resonator circuit XCIN Rf CCIN XCOUT Rd CCOUT XIN XOUT Open External oscillation circuit VCC VSS Fig. 52 External clock input circuit 45 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCIN XCOUT XIN XOUT Internal system clock selection bit (Note) Timer 1 count source selection bit "1" Timer 1 "0" Timer 2 count source selection bit "0" Timer 2 "1" Low-speed mode "0" 1/2 "1" Middle-/High-speed mode 1/4 1/2 Main clock division ratio selection bit Middle-speed mode "1" "0" High-speed mode or Low-speed mode Timing (Internal clock) Main clock stop bit Q S R WIT instruction S R Q Q S STP instruction STP instruction R Reset Interrupt disable flag I Interrupt request Note: When selecting the XC oscillation, set the port XC switch bit to "1" . Fig. 53 Clock generating circuit block diagram 46 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset Middle-speed mode (f() =1 MHz) CM7=0(8 MHz selected) CM6=1(Middle-speed) CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped) CM6 "1" High-speed mode (f() =4 MHz) "0" CM7=0(8 MHz selected) CM6=0(High-speed) CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped) CM " "1 M6 C " "1 4 "0 " "0 " CM4 "1" " "0 " Middle-speed mode (f() =1 MHz) CM7=0(8 MHz selected) CM6=1(Middle-speed) CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) CM6 "1" High-speed mode (f() =4 MHz) "0" CM7=0(8 MHz selected) CM6=0(High-speed) CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) "0" CM7 "1" Low-speed mode (f() =16 kHz) CM7=1(32 kHz selected) CM6=1(Middle-speed) CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) CM6 "1" Low-speed mode (f() =16 kHz) "0" CM7=1(32 kHz selected) CM6=0(High-speed) CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) CM7 "1" "0" CM4 "1" C "0 M4 " CM "1 "6 "1 "0" "0" b7 b4 CPU mode register (CPUM : address 003B16) CM " "1 M6 C " "1 5 "0 " " 0" "1 " C "0 M5 " CM 6 "0" "0" CM5 "1" " "0 " Low-power dissipation mode (f() =16 kHz) CM7=1(32 kHz selected) CM6=1(Middle-speed) CM5=1(8 MHz stopped) CM4=1(32 kHz oscillating) CM6 "1" "0" Low-power dissipation mode (f() =16 kHz) CM7=1(32 kHz selected) CM6=0(High-speed) CM5=1(8 MHz stopped) CM4=1(32 kHz oscillating) Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3 : Timer and LCD operate in the wait mode. 4 : When the stop mode is ended, wait time can be set by connecting timer 1 and timer 2 in middle-/high-speed mode. 5 : When the stop mode is ended, wait time can be set by connecting timer 1 and timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle-/high-speed mode. 7 : The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the XCIN pin. indicates the internal clock. Fig. 54 State transitions of system clock CM5 "1" "1 CM4 : Port Xc switch bit 0: I/O port function 1: XCIN-XCOUT oscillating function CM5 : Main clock (XIN-XOUT) stop bit 0: Oscillating 1: Stopped CM6 : Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM7 : Internal system clock selection bit 0: XIN-XOUT selected (middle-/high-speed mode) 1: XCIN-XCOUT selected (low-speed mode) 47 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1". After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to "1". Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. In serial I/O2, the SOUT2 pin goes to high impedance state after transmission is completed. Interrupt The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is at least 500 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion. Decimal Calculations * To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock is half of the XIN frequency. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1). Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direction registers. 48 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies) ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 10 Special programming adapter Package 100PFB-A 100P6Q-A 100P6S-A 100D0 Name of Programming Adapter Under development (PCA4738H-100A) PCA4738G-100A PCA4738F-100A PCA4738L-100A DATA REQUIRED FOR ROM WRITING ORDERS The following are necessary when ordering a ROM writing: (1) ROM Writing Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies) The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 55 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours. Fig. 55 Programming and testing of One Time PROM version 49 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Table 11 Absolute maximum ratings Symbol VCC VI VI VI VI VI VI VI VI VO VO VO VO VO VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P41-P47, P50-P57, P60-P67 Input voltage P40, P71-P77 Input voltage P70 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage C1, C2 Input voltage RESET, XIN Output voltage C1, C2 Output voltage P00-P07, P10-P15, P30-P37 Output voltage P16, P17, P20-P27, P41-P47, P50-P57, P60-P67, P80, P81 Output voltage P40, P71-P77 Output voltage VL3 Output voltage VL2, SEG0-SEG17 Output voltage XOUT Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 to 7.0 -0.3 to VCC +0.3 -0.3 to 7.0 -0.3 to VCC +0.3 -0.3 to VL2 VL1 to VL3 VL2 to 7.0 -0.3 to 7.0 -0.3 to VCC +0.3 -0.3 to 7.0 -0.3 to VCC -0.3 to VL3 -0.3 to VCC +0.3 -0.3 to 7.0 -0.3 to 7.0 -0.3 to VL3 -0.3 to VCC +0.3 300 -20 to 85 -40 to 125 Unit V V V V V V V V V V V V V V V V V mW C C All voltages are based on VSS. Output transistors are cut off. At output port At segment output Ta = 25C RECOMMENDED OPERATING CONDITIONS Table 12 Recommended operating conditions (VCC = 2.5 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Symbol Parameter High-speed mode f(XIN) = 8 MHz Middle-speed mode f(XIN) = 8 MHz Low-speed mode Min. 4.0 2.2 2.2 2.7 0 AVSS P10-P17, P40, P43, P45, P47, P50-P53, P64-P67, P71-P77 P41, P42, P44, P46, P54, P55, P57, P60, P70 0.7 VCC 0.8 VCC 0.8 VCC 0.8 VCC P10-P17, P40, P43, P45, P47, P50-P53, P64-P67, P71-P77 P41, P42, P44, P46, P54, P55, P57, P60, P70 0 0 0 0 VCC VCC VCC VCC VCC 0.3 VCC 0.2 VCC 0.2 VCC 0.2 VCC Limits Typ. 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 VCC+0.3 Unit VCC VSS VREF AVSS VIA VIH VIH VIH VIH VIL VIL VIL VIL Power source voltage V V V V V V V V V V V V V Power source voltage A-D, D-A conversion reference voltage Analog power source voltage Analog input voltage AN0-AN7 "H" input voltage P00-P07, P56, P61, "H" input voltage P20-P27, P62, P63, RESET "H" input voltage XIN "H" input voltage "L" input voltage P00-P07, P56, P61, "L" input voltage P20-P27, P62, P63, "L" input voltage RESET "L" input voltage XIN 50 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 13 Recommended operating conditions (VCC = 2.2 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Symbol IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) "H" total peak output current "H" total peak output current "L" total peak output current "L" total peak output current "L" total peak output current "H" total average output current "H" total average output current "L" total average output current "L" total average output current "L" total average output current "H" peak output current "H" peak output current "L" peak output current "L" peak output current "L" peak output current "H" average output current "H" average output current "L" average output current "L" average output current "L" average output current Parameter P00-P07, P10-P17, P20-P27, P30-P37 (Note 1) P41-P47, P50-P57, P60-P67 (Note 1) P00-P07, P10-P17, P20-P27, P30-P37 (Note 1) P41-P47, P50-P57, P60-P67 (Note 1) P40, P71-P77 (Note 1) P00-P07, P10-P17, P20-P27, P30-P37 (Note 1) P41-P47, P50-P57, P60-P67 (Note 1) P00-P07, P10-P17, P20-P27, P30-P37 (Note 1) P41-P47, P50-P57, P60-P67 (Note 1) P40, P71-P77 (Note 1) P00-P07, P10-P15, P30-P37 (Note 2) P16, P17, P20-P27, P41-P47, P50-P57, P60-P67 (Note 2) P00-P07, P10-P15, P30-P37 (Note 2) P16, P17, P20-P27, P41-P47, P50-P57, P60-P67 (Note 2) P40, P71-P77 (Note 2) P00-P07, P10-P15, P30-P37 (Note 3) P16, P17, P20-P27, P41-P47, P50-P57, P60-P67 P00-P07, P10-P15, P30-P37 (Note 3) P16, P17, P20-P27, P41-P47, P50-P57, P60-P67 (Note 3) P40, P71-P77 (Note 3) Min. Limits Typ. Max. -20 -20 20 20 80 -10 -10 10 10 40 -1.0 -5.0 5.0 10 20 -0.5 -2.5 2.5 5.0 10 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 51 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 14 Recommended operating conditions (Mask ROM version) (VCC = 2.2 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Symbol f(CNTR0) f(CNTR1) Parameter Input frequency for timers X and Y (duty cycle 50%) Test conditions (4.0 V VCC 5.5 V) (2.2 V VCC 4.0 V) High-speed mode (4.0 V VCC 5.5 V) High-speed mode (2.2 V VCC 4.0 V) Middle-speed mode Min. Limits Typ. Max. 4.0 Unit MHz (10!VCC -4)/9 MHz 8.0 MHz f(XIN) Main clock input oscillation frequency (Note 1) f(XCIN) Sub-clock input oscillation frequency (Notes 1, 2) (20!VCC -8)/9 MHz 8.0 MHz 32.768 50 kHz Notes1: When the oscillation frequency has a duty cycle of 50%. 2: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. Table 15 Recommended operating conditions (PROM version) (VCC = 2.5 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Symbol f(CNTR0) f(CNTR1) Parameter Input frequency for timers X and Y (duty cycle 50%) Test conditions (4.0 V VCC 5.5 V) (2.5 V VCC 4.0 V) High-speed mode (4.0 V VCC 5.5 V) High-speed mode (2.5 V VCC 4.0 V) Middle-speed mode Min. Limits Typ. Max. 4.0 Unit MHz (2!VCC) -4 MHz 8.0 MHz f(XIN) Main clock input oscillation frequency (Note 1) f(XCIN) Sub-clock input oscillation frequency (Notes 1, 2) (4!VCC) -8 MHz 8.0 MHz 32.768 50 kHz Notes1: When the oscillation frequency has a duty cycle of 50%. 2: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 52 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 16 Electrical characteristics (VCC =4.0 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Symbol Parameter "H" output voltage P00-P07, P10-P15, P30-P37 "H" output voltage P16, P17, P20-P27, P41-P47, P50-P57, P60-P67 (Note 1) Test conditions IOH = -1 mA IOH = -0.25 mA VCC = 2.2 V IOH = -5 mA IOH = -1.5 mA IOH = -1.25 mA VCC = 2.2 V IOL = 5 mA IOL = 1.5 mA IOL = 1.25 mA VCC = 2.2 V IOL = 10 mA IOL = 3.0 mA IOL = 2.5 mA VCC = 2.2 V IOL = 10 mA IOL = 5 mA VCC = 2.2 V Limits Min. VCC-2.0 VCC-0.8 VCC-2.0 VCC-0.5 VCC-0.8 2.0 0.5 0.8 2.0 0.5 0.8 0.5 0.3 0.5 0.5 0.5 5.0 5.0 4.0 -5.0 -60.0 -5.0 -120.0 -20.0 -240.0 -40.0 -5.0 -5.0 -4.0 -60.0 -5.0 -120.0 -20.0 -240.0 -40.0 5.0 -5.0 Typ. Max. Unit V V V V V V V V V V V V V V V V A A A A A A A A A A A A A VOH VOH VOL "L" output voltage P00-P07, P10-P15, P30-P37 VOL "L" output voltage P16, P17, P20-P27, P41-P47, P50-P57, P60-P67 "L" output voltage P40, P71-P77 VOL VT+ - VT- VT+ - VT- VT+ - VT- IIH IIH IIH Hysteresis INT0-INT2, ADT, CNTR0, CNTR1, P20-P27 Hysteresis SCLK, RXD Hysteresis RESET "H" input current P00-P07, P10-P17, P20-P27, P40-P47, VI = VCC P50-P57, P60-P67, P70-P77 "H" input current "H" input current RESET XIN VI = VCC VI = VCC VI = VSS Pull-ups "off" VCC = 5 V, VI = VSS Pull-ups "on" VCC = 2.2 V, VI = VSS Pull-ups "on" VI = VSS VI = VSS VCC = 5.0 V, VO = VCC, Pull-ups "on" Output transistors "off" VCC = 2.2 V, VO = VCC, Pull-ups "on" Output transistors "off" VO = VCC, Pull-ups "off" Output transistors "off" VO = VSS, Pull-ups "off" Output transistors "off" IIL "L" input current P00-P07, P10-P17, P20-P27,P40-P47, P50-P57, P60-P67, P70-P77 IIL IIL IIL ILOAD "L" input current "L" input current "L" input current P70 RESET XIN Output load current P30-P37 ILEAK Output leak current P30-P37 53 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 17 Electrical characteristics (VCC =2.2 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Symbol VRAM Parameter RAM retention voltage Test conditions At clock stop mode * High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors "off" A-D conver ter in operating * High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors "off" A-D conver ter in operating * Low-speed mode, VCC = 5 V, Ta 55C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "off" * Low-speed mode, VCC = 5 V, Ta = 25C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "off" * Low-speed mode, VCC = 3 V, Ta 55C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "off" * Low-speed mode, VCC = 3 V, Ta 25C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "off" All oscillation stopped (in STP state) Output transistors "off" VL1 IL1 Power source voltage Power source current (VL1) (Note) When using voltage multiplier VL1 = 1.8 V VL1 < 1.3 V Ta = 25 C Ta = 85 C 1.3 1.8 3.0 10.0 1.6 3.2 mA 6.4 13 mA Min. 2.0 Limits Typ. Max. 5.5 Unit V 35 70 A ICC Power source current 20 40 A 15.0 22.0 A 4.5 9.0 A 0.1 1.0 10.0 2.3 6.0 50.0 A V A Note: When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is "1". 54 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 18 A-D converter characteristics (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, 4 MHz f(XIN) 8 MHz, in middle/high-speed mode unless otherwise noted) Symbol - - tCONV RLADDER IVREF IIA Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current Analog port input current Test conditions Min. Limits Typ. Max. 10 2.5 4.0 31 (Note) 35 150 0.5 200 5.0 Unit Bits LSB LSB s k A A VCC VREF = 4 V VCC VREF = 2.7 V f(XIN) = 4 MHz 30.5 VREF = 5 V 50 Note: When an internal trigger is used in middle-speed mode, it is 34 s. Table 19 D-A converter characteristics (VCC = 2.2 to 5.5 V, VCC = VREF, VSS = AVSS = 0 V, Ta = -20 to 85C, in middle/high-speed mode unless otherwise noted) Symbol - - tsu RO IVREF Resolution Absolute accuracy Setting time Output resistor Reference power source input current VCC = VREF = 5 V VCC = VREF = 2.7 V 1 (Note) 3 2.5 Parameter Test conditions Min. Limits Typ. Max. 8 1.0 2.0 4 6.0 Unit Bits % % s k mA Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being "0016", and excluding currents flowing through the A-D resistance ladder. 55 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 20 Timing requirements 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1) twH(SCLK1) twL(SCLK1) tsu(RXD-SCLK1) th(SCLK1-RXD) tc(SCLK2) twH(SCLK2) twL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input "L" pulse width Main clock input cycle time (XIN input) Main clock input "H" pulse width Main clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT2 input "H" pulse width INT0 to INT2 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time (Note) Serial I/O2 clock input "H" pulse width (Note) Serial I/O2 clock input "L" pulse width (Note) Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 125 45 40 250 105 105 80 80 800 370 370 220 100 1000 400 400 200 200 Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: When bit 6 of address 001A16 is "1". Divide this value by four when bit 6 of address 001A16 is "0". Table 21 Timing requirements 2 (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1) twH(SCLK1) twL(SCLK1) tsu(RXD-SCLK1) th(SCLK1-RXD) tc(SCLK2) twH(SCLK2) twL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input "L" pulse width Main clock input cycle time (XIN input) Main clock input "H" pulse width Main clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT2 input "H" pulse width INT0 to INT2 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time (Note) Serial I/O2 clock input "H" pulse width (Note) Serial I/O2 clock input "L" pulse width (Note) Serial I/O2 input set up time Serial I/O2 input hold time Limits Min. Typ. 2 125 45 40 900/(VCC-0.4) tc(CNTR)/2-20 tc(CNTR)/2-20 230 230 2000 950 950 400 200 2000 950 950 400 300 Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: When bit 6 of address 001A16 is "1". Divide this value by four when bit 6 of address 001A16 is "0". 56 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 22 Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol twH(SCLK1) twL(SCLK1) td(SCLK1-TXD) tv(SCLK1-TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Limits Min. tC (SCLK1)/2-30 tC (SCLK1)/2-30 -30 30 30 tC (SCLK2)/2-160 tC (SCLK2)/2-160 0.2 ! tC (SCLK2) 0 10 10 40 30 30 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 140 Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: XOUT and XCOUT pins are excluded. Table 23 Switching characteristics 2 (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol twH(SCLK1) twL(SCLK1) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Min. tC (SCLK1)/2-50 tC (SCLK1)/2-50 -30 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns td(SCLK1-TXD) tv(SCLK1-TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) 350 50 50 tC (SCLK2)/2-240 tC (SCLK2)/2-240 0.2 ! tC (SCLK2) 0 20 20 50 50 50 Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: XOUT and XCOUT pins are excluded. 57 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Measurement output pin 100 pF Measurement output pin 100 pF 1 k CMOS output N-channel open-drain output (Note) Note : When bit 4 of the UART control register (address 001B16) is "1". (N-channel open-drain output mode) Fig. 56 Circuit for measuring output switching characteristics 58 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER tC (CNTR) tWH (CNTR) CNTR0, CNTR1 0.8VCC 0.2VCC tWL (CNTR) tWH (INT) INT0-INT3 0.8VCC 0.2VCC tWL (INT) tW (RESET) RESET 0.2VCC 0.8VCC tC (XIN) tWH (XIN) XIN 0.8VCC 0.2VCC tWL (XIN) tf SCLK 0.2VCC tWL (SCLK) tC (SCLK) tr 0.8VCC tWH (SCLK) tsu (RXD-SCLK) RXD 0.8VCC 0.2VCC td (SCLK-TXD) TXD th (SCLK-RXD) tv (SCLK-TXD) Fig. 57 Timing diagram 59 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MASK ROM ORDER CONFIRMATION FORM GZZ-SH52-92B<85A0> Mask ROM number Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor g Customer g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Product name: M38277M8MXXXFP M38277M8MXXXGP M38277M8MXXXHP Checksum code for entire EPROM EPROM type (indicate the type used) (hexadecimal notation) 27512 EPROM address 000016 000F16 001016 Product name ASCII code : `M38277M8M' In the address space of the microcomputer, the internal ROM area is from address 808016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. 807F16 808016 Data ROM 32K-130 bytes FFFD16 FFFE16 FFFF16 (1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38277M8M" must be entered in addresses 000016 to 000816. And set data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hesadecimal notation. (1/2) Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38277M8MXXXFP/GP/HP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature Address 000016 000116 000216 000316 000416 000516 000616 000716 `M' = 4D16 `3' = 3316 `8' = 3816 `2' = 3216 `7' = 3716 `7' = 3716 `M' = 4D16 `8' = 3816 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ` M ' =4D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 60 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH52-92B<85A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38277M8MXXXFP/GP/HP MITSUBISHI ELECTRIC We recommend the use of the following pseudo-command to set the start address of the assembier source program because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM. EPROM type The pseudo-command 27512 *=$0000 .BYTE `M38277M8M' Note: If the name of the product written to the EPROMs does not match the name of the mask ROM confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (100P6S for M38277M8MXXXFP, 100P6Q for M38277M8MXXXGP, 100PFB for M38277M8MXXXHP) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator Quartz crystal External clock input At what frequency? (2) How will you use the XCIN-XCOUT oscillator? Ceramic resonator Other ( At what frequency? g 4. Comments ) f(XCIN) = MHz Quartz crystal Other ( f(XIN) = ) MHz (2/2) 61 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ROM PROGRAMMING CONFIRMATION FORM GZZ-SH51-93B<85A0> ROM number 740 FAMILY ROM PROGRAMMING CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M38279EF-XXXFP/GP/HP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor g Customer g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the programming data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Product name: M38279EF-XXXFP M38279EF-XXXGP M38279EF-XXXHP Checksum code for entire EPROM EPROM type (indicate the type used) (hexadecimal notation) 27512 EPROM address 000016 000F16 001016 Product name ASCII code : `M38279EF-' In the address space of the microcomputer, the internal ROM area is from address 108016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16. 107F16 108016 FFFD16 FFFE16 FFFF16 Data ROM 60K-130 bytes (1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38279EF-" must be entered in addresses 000016 to 000816. And set data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hesadecimal notation. (1/2) Address 000016 000116 000216 000316 000416 000516 000616 000716 `M' = 4D16 `3' = 3316 `8' = 3816 `2' = 3216 `7' = 3716 `9' = 3916 `E' = 4516 `F' = 4616 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ` - ' =2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 62 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH51-93B<85A0> ROM number 740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38279EF-XXXFP/GP/HP MITSUBISHI ELECTRIC We recommend the use of the following pseudo-command to set the start address of the assembier source program because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM. EPROM type The pseudo-command 27512 *=$0000 .BYTE `M38279EF-' Note: If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (100P6S for M38279EF-XXXFP, 100P6Q for M38279EF-XXXGP, 100PFB for M38279EF-XXXHP) and attach it to the ROM programming confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator Quartz crystal External clock input At what frequency? (2) How will you use the XCIN-XCOUT oscillator? Ceramic resonator Other ( At what frequency? g 4. Comments ) f(XCIN) = MHz Quartz crystal Other ( f(XIN) = ) MHz (2/2) 63 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 100P6S-A EIAJ Package Code QFP100-P-1420-0.65 HD D 100 1 81 80 Plastic 100pin 14!20mm body QFP JEDEC Code - Weight(g) 1.58 Lead Material Alloy 42 MD e b2 I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME Dimension in Millimeters Min Nom Max - - 3.05 0.1 0.2 0 2.8 - - 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.65 - - 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 - - 0.1 - - 0 10 - 0.35 - - - - 1.3 - - 14.6 - - 20.6 30 51 31 50 HE E A L1 A2 b A1 e y F Detail F 100P6Q-A EIAJ Package Code LQFP100-P-1414-0.50 JEDEC Code - Weight(g) Lead Material Cu Alloy c L Plastic 100pin 14!14mm body LQFP MD D 100 76 1 75 b2 I2 Recommended Mount Pad HE E Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME 25 51 26 50 A e F L1 y A1 b L Detail F Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 1.4 - - 0.13 0.18 0.28 0.105 0.125 0.175 13.9 14.0 14.1 13.9 14.0 14.1 0.5 - - 15.8 16.0 16.2 15.8 16.0 16.2 0.3 0.5 0.7 1.0 - - 0.1 - - 0 10 - 0.225 - - - - 1.0 - - 14.4 - - 14.4 A2 64 c ME HD e ME MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 100PFB-A EIAJ Package Code TQFP100-P-1212-0.40 HD D 100 76 Plastic 100pin 12!12mm body TQFP JEDEC Code - Weight(g) Lead Material Cu Alloy e MD Under Development ME 75 1 b2 l2 Recommended Mount Pad Dimension in Millimeters Min Nom Max - - 1.2 0.1 0.15 0.05 1.0 - - 0.13 0.18 0.23 0.105 0.125 0.175 11.9 12.0 12.1 11.9 12.0 12.1 0.4 - - 13.8 14.0 14.2 13.8 14.0 14.2 0.4 0.5 0.6 1.0 - - 0.08 - - 0 8 - 0.225 - - 1.0 - - 12.4 - - - - 12.4 HE E Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME 25 51 26 50 A L1 e F A2 A1 b y L Detail F 100D0 EIAJ Package Code - JEDEC Code - Weight(g) c Glass seal 100pin QFN 5.0MAX 21.00.13 3.5TYP 51 50 18.850.15 0.65TYP 0.45TYP 80 81 0.65TYP 1.075TYP 31 100 30 1 0.35TYP INDEX 1.075TYP 0.65TYP 12.350.15 15.60.13 65 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 100P6S (100-PIN QFP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 80 81 51 50 Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit) 100 31 1 30 B. Customer's Parts Number + Mitsubishi catalog name 80 81 51 50 100 31 1 30 Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's Parts Number can be up to 14 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c), (periods), (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required . , C. Special Mark Required 80 81 51 50 100 31 Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required 1 30 66 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 100P6Q (100-PIN LQFP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 75 51 76 50 Mitsubishi IC catalog name Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit) 100 26 1 25 B. Customer's Parts Number + Mitsubishi catalog name 75 51 76 50 Mitsubishi lot number (6-digit or 7-digit) 100 26 1 25 Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's Parts Number can be up to 12 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c), (periods), (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required . , C. Special Mark Required 75 51 76 50 Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required 100 26 1 25 67 MITSUBISHI MICROCOMPUTERS 3827 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 100PFB (100-PIN TQFP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 75 51 76 50 Mitsubishi IC catalog name Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit) 100 26 1 25 B. Customer's Parts Number + Mitsubishi catalog name 75 51 76 50 Mitsubishi lot number (6-digit or 7-digit) 100 26 1 Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's Parts Number can be up to 10 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c), (periods), (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required . , 25 5 : The allocation of Mitsubishi IC catalog name and Mitsubishi Product number depend on the Mitsubishi IC catalog name's characters, and requiring Mitsubishi logo or not. C. Special Mark Required 75 51 76 50 Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required 100 26 1 25 68 Keep safety first in your circuit designs! * Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials * * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. * * * * (c) 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Jun. 1998. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 First Edition 3827 GROUP DATA SHEET Revision Description Rev. date 980602 (1/1) |
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